1. Field of the Invention
The present invention relates to a glitch removal system, and in particular to a glitch free clock multiplexer circuit and a method thereof which are capable of removing a glitch of a clock signal occurred in a clock conversion due to a timing difference between asynchronous clock signals and a selected signal.
2. Description of the Prior Art
Generally, a customized ASIC (application specific integrated circuit) designed and produced for a specific user requires lots of clocks and clock conversions in system operation.
FIG. 1 is an exemplary view illustrating a clock selection method of the conventional multiplexer. As depicted in FIG. 1, the conventional multiplexer 1 receives asynchronous signals (Clock_A, Clock_B) and outputs one of the signals according to an external selection signal (Sel).
A timing of a clock using the multiplexer 1 will be described.
FIG. 2 is a timing chart illustrating a clock selection method using the conventional multiplexer. As depicted in FIG. 2, when an external selection signal is in a low state, the multiplexer 1 outputs a clock signal A (Clock_A), when an external selection signal is in a high state, the multiplexer 1 outputs a clock signal B (Clock_B).
However, while the clock signal is changed according to the external selection signal, a glitch 3 may occur or a duty 5 of the clock may be changed due to a timing difference between the asynchronous clock signals (Clock_A, Clock_B) and the external selection signal.
Accordingly, when a clock signal is changed by the conventional clock selection method, because a glitch may occur or a duty of a clock may be changed due to a timing difference between a plurality of asynchronous clock signals and an external selection signal, a system collision caused by an error output or an error operation may occur.
Accordingly, it is an object of the present invention to provide a glitch free clock multiplexer circuit and a method thereof which are capable of outputting a glitch free clock signal by receiving asynchronous clock signals, comparing a delay signal delayed for a certain clock cycle with a count value provided from a user, outputting a first control signal (Sel_clock) corresponded to a comparison result and outputting a second control signal (enable) for controlling the first control signal in a logic low state.
In order to achieve the above-mentioned object, a glitch free clock multiplexer circuit in accordance with the present invention includes a delay unit for receiving asynchronous clock signals (Clock A, Clock B) and an external selection signal (Sel) and outputting a delay signal by delaying the clock signal selected by the external selection signal (Sel) for a certain clock cycle, a state region transition generating unit for comparing the delay signal with a count value provided from a user, outputting a first control signal (Sel_clock) according to a comparison result and outputting a second control signal (enable) for controlling the first control signal in a logic low state, and a glitch removal unit for outputting a clock output signal (Clock_out) by performing an AND operation of a temporary clock signal (Temp_clock) selected by the first control signal and a third control signal generated by delaying the second control signal (enable) for a certain clock cycle.
In order to achieve the above-mentioned object, a glitch free clock method of a glitch free clock multiplexer circuit in accordance with the present invention includes receiving asynchronous clock signals and an external selection signal (Sel) and outputting a delay signal generated by delaying the clock signal for a certain clock cycle, comparing the delay signal with a count value provided from a user and outputting a first control signal (Sel_Clock) and a second control signal (enable) corresponded to the count value, and outputting a clock output signal (Clock_out) by performing an AND operation of a temporary clock signal (Temp_clock) selected by the first control signal (Sel_clock) and a third control signal (enable_2delay) generated by delaying the second control signal (enable) for a certain clock cycle when it is in a logic high state.